Parasitic inductance reduction for multilayered board layout designs with semiconductor devices
US9035417B2 · kind B2 · utility
5Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Dec 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10166
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.