Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
US9035686B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Oct 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.