Circuit arrangement with a first semiconductor device and with a plurality of second semiconductor devices
US9035690B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2012 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/687
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.