Phase change memory with bit line matching
US9036408B1 · kind B1 · utility
9Cited by
1References
20Claims
0Family size
Inventors
Key dates
| Filing date | Aug 27, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Jan 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, circuits, and systems for phase change memories. A matching bit line, on which no data-containing PCM cells have been selected, is used to cancel out time-dependent current components due to parasitic capacitive and leakage resistance loading of bit lines. This can effectively allow direct comparison of the current from the phase change memory cell to the desired reference current, at a time before the voltage of the first bit line permits stable operations using DC comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.