Ultra-deep power-down mode for memory devices
US9037890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2012 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Jun 27, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.