Apparatus and method for partial memory mirroring
US9037903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Jul 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1666
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for performing partial memory mirroring operations. For example, one embodiment of a processor comprises: a processor core for generating a read or write transaction having a system memory address; a home agent identified to service the read or write transaction based on the system memory address; one or more target address decoders (TADs) associated with the home agent to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region, wherein: if the system memory address is within a mirrored memory region, then the one or more TADs identifying multiple mirrored memory channels for the read or write transaction; and if the system memory address is not within a mirrored memory region, then the one or more TADs identifying a single memory channel for the read or write transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.