System and method for containing analog verification IP
US9038008B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2014 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Mar 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.