Anti-fuses on semiconductor fins
US9040370B2 · kind B2 · utility
6Cited by
1References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Feb 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.