Patent · US Active

Releasable buried layer for 3-D fabrication and methods of manufacturing

US9040390B2 · kind B2 · utility

1Cited by
11References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 30, 2012
Grant dateMay 26, 2015
Priority date
Expiry dateJun 20, 2033

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10S438/976
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.