Gate electrode with a shrink spacer

US9040405B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Tom Hasche · Dresden, DE
• Sven Beyer · Dresden, DE
• Gerhard Lembach · Rohrbach, DE
• Alexander Ebermann · Dresden, DE

Key dates

• Filing date: Oct 1, 2013
• Grant date: May 26, 2015
• Expiry date: Oct 1, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/947
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.