Nonvolatile memory structure
US9041089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Dec 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.