Power transistor and associated method for manufacturing
US9041102B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Dec 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
Abstract
The present disclosure discloses a lateral transistor and associated method for making the same. The lateral transistor comprises a gate formed over a first portion of a thin gate dielectric layer, and a field plate formed over a thick field dielectric layer and extending atop a second portion of the thin gate dielectric layer. The field plate is electrically isolated from the gate by a gap overlying a third portion of the thin gate dielectric layer and is electrically coupled to a source region. The lateral transistor according to an embodiment of the present invention may have reduced gate-to-drain capacitance, low specific on-resistance, and improved hot carrier lifetime.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.