Land grid array package capable of decreasing a height difference between a land and a solder resist
US9041181B2 · kind B2 · utility
0Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2011 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Feb 5, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/948
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.