Through silicon via wafer and methods of manufacturing
US9041210B2 · kind B2 · utility
0Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Dec 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.