Delay compensation circuit
US9041366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jul 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/04123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device (200) includes a circuit (202) and a driver stage (204) therefor. The circuit includes two sub-circuits (231 and 232). The driver stage includes switcher logic (206) that produces signals that control switching on and off of the sub-circuits. The switcher logic also produces other signals in advance of the signals that control the switching of the sub-circuits. The driver stage includes delay compensations circuits (221 and 222), coupled to the switcher logic and to the circuit, that produce timing signals for the switcher logic. The timing signals are closely aligned with moments that a changing voltage at a node between the sub-circuits passes through threshold voltages. The timing signals compensate for all delays of signals through the device such that a period that both sub-circuits are off is minimized, while ensuring that both sub-circuits are not on at a same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.