Static image retiling and power management method and circuit
US9041720B2 · kind B2 · utility
3Cited by
5References
22Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jun 13, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes memory retiling methods which distribute image information among a plurality of memory channels producing reconfigured image information distributed among a subset of the plurality of memory channels allowing memory channels outside of the subset to be placed into a power save mode to reduce power consumption. Additional methods are disclosed for further reductions in power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.