Optimizing a cache back invalidation policy
US9043556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Dec 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, a system and a computer program product for enhancing a cache back invalidation policy by utilizing least recently used (LRU) bits and presence bits in selecting cache-lines for eviction. A cache back invalidation (CBI) utility evicts cache-lines by using presence bits to avoid replacing a cache-line in a lower level cache that is also present in a higher level cache. Furthermore, the CBI utility selects the cache-line for eviction from an LRU group. The CBI utility ensures that dormant cache-lines in the higher level caches do not retain corresponding presence bits set in the lower level caches by unsetting the presence bits in the lower level cache when a line is replaced in the higher level cache. Additionally, when a processor core becomes idle, the CBI utility invalidates the corresponding higher level cache by unsetting the corresponding presence bits in the lower level cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.