Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9043580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Dec 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30196
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.