Banking of reliability metrics
US9043659B2 · kind B2 · utility
2Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jul 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.