Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor
US9043795B2 · kind B2 · utility
5Cited by
5References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 11, 2008 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Aug 24, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.