Method and apparatus for limiting access to an integrated circuit (IC)
US9046570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2012 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Apr 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.