Patent · US Active

Power savings apparatus and method for memory device using delay locked loop

US9047237B2 · kind B2 · utility

1Cited by

1References

21Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Qamrul Hasan · Santa Clara, US
Clifford Alan Zitlaw · San Jose, US
Stephan Rosner · Campbell, US
Sylvain Dubois · Vence, FR

Key dates

Filing date	Aug 3, 2012
Grant date	Jun 2, 2015
Priority date	—
Expiry date	Jun 4, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.