Circuit for concurrent read operation and method therefor
US9047939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.