Self-alignment structure for wafer level chip scale package
US9048149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2013 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.