Testing of semiconductor components and circuit layouts therefor

US9048150B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Michael Roehner · Munich, DE
• Stefano Aresu · Munich, DE
• Markus Zannoth · Munich, DE

Key dates

• Filing date: Dec 23, 2013
• Grant date: Jun 2, 2015
• Expiry date: Dec 23, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/37001
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device within and/or over a substrate. A first voltage is applied to a first node coupled to a component to be tested in the substrate and a test voltage at a pad coupled to the component to be tested through a second node. The test voltage has a peak voltage higher than the first voltage. The component to be tested is coupled between the first node and the second node. A leakage current is measured through the component to be tested in response to the test voltage. After performing the test, the second node is connected to a functional block in the substrate. The first node is coupled to a third node coupled to the functional block.