Profile pre-shaping for replacement poly gate interlayer dielectric
US9048185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2014 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Aug 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.