Circuitry to facilitate testing of serial interfaces
US9049020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2010 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Feb 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/243
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.