Zero-latency network on chip (NoC)
US9049124B2 · kind B2 · utility
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Key dates
| Filing date | Oct 14, 2009 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Dec 29, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.