Packet switch based logic replication
US9052357B2 · kind B2 · utility
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18References
22Claims
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Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Jan 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for debugging comprising configuring a switching logic mapping source subchannels to destination subchannels, as virtual channels to forward the packets from the source subchannels to the destination subchannels. The method further comprising configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronously with the plurality of clock domains with the delay period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.