Multi-threaded system for performing atomic binary translations
US9053035B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45558
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.