Cache coherence directory in multi-processor architectures
US9053057B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Dec 16, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described for a cache coherence directory in multi-processor architectures. In an example, a directory in a die may receive a request for a particular block. The directory may determine a block aging threshold relating to a likelihood that data blocks, including the particular data block, are stored in one or more caches in the die. The directory may further analyze a memory to identify a particular cache indicated as storing the particular data block and identify a number of cache misses for the particular cache. The directory may identify a time when an event occurred for the particular data block and determine whether to send the request for the particular data block to the particular cache based on the aging threshold, the time of the event, and the number of cache misses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.