NAND flash memory interface
US9053066B2 · kind B2 · utility
12Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Nov 6, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory chip has a configurable interface that can communicate with a NAND flash memory controller using either parallel communication or serial communication. Serial communication requires fewer channels. Control information from the NAND flash memory controller uses a small number of channels. Double Data Rate (DDR) communication provides serial communication with adequate data transfer speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.