Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
US9053270B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2014 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Jun 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.