Integrated circuit reset system modification tool
US9053271B1 · kind B1 · utility
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5References
19Claims
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Key dates
| Filing date | Feb 6, 2014 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Feb 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic design automation (EDA) tool that analyzes a circuit design to identify sequential elements (flip-flops) that do not need to be reset, for example, because they do not need to be initialized in order to be in a known state, and converts the identified sequential elements to non-resettable circuits, which saves power and area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.