Patent · US Active

Dual-structure clock tree synthesis (CTS)

US9053281B2 · kind B2 · utility

1Cited by

5References

15Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Xiaojun Ma · Yokohama, JP
Min Pan · Hangzhou City, CN
Aiqun Cao · Sunnyvale, US
Cheng Ding · San Jose, US

Key dates

Filing date	Mar 20, 2014
Grant date	Jun 9, 2015
Priority date	—
Expiry date	Mar 20, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of the upper-level clock tree to a set of clock sinks. The lower-level clock tree can be optimized to reduce latency, power consumption, and/or area.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.