Triggered cell annihilation for resistive switching memory devices
US9053789B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 10, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device, can include resistive memory cells configured to be programmed to a low resistance state by application of a first voltage, and to be erased to a high resistance state by application of a second voltage; a detector configured to detect when at least one resistive switching memory cell is to be rendered inoperable; and a program/erase controller configured to render the at least one resistive switching memory cell inoperable by application of a third voltage during a program/erase operation, where the third voltage is greater in absolute value than the first or second voltage, and where the at least one resistive switching memory cell rendered inoperable remains in the low/high resistance state after subsequent erase/program operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.