Circuit in dynamic random access memory devices
US9053815B2 · kind B2 · utility
16Cited by
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7Claims
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Key dates
| Filing date | May 28, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Sep 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.