Methods of forming patterns and methods of manufacturing semiconductor devices using the same
US9054054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2011 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Nov 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/47
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.