Noise attenuation wall
US9054096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | May 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.