High electron mobility transistor structure and method
US9054167B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.