HEMT semiconductor device

US9054171B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Tetsuya Ohno · Kawasaki, JP
• Yasunobu Saito · Tokyo, JP
• Hidetoshi Fujimoto · Yokohama, JP
• Akira Yoshioka · Yokohama, JP
• Takeshi Uchihara · Osaka, JP
• Toshiyuki Naka · Yokohama, JP
• Takaaki Yasumoto · Yokohama, JP
• Naoko Yanase · Kawasaki, JP
• Shingo Masuko · Suzaka, JP
• Tasuku ONO

Key dates

• Filing date: Mar 7, 2014
• Grant date: Jun 9, 2015
• Expiry date: Mar 7, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/117

Abstract

In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.