Patent · US Active

Methodology of forming CMOS gates on the secondary axis using double-patterning technique

US9054214B1 · kind B1 · utility

7Cited by

3References

19Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Gregory Charles Baldwin · Plano, US
Scott Jessen · Allen, US

Key dates

Filing date	Dec 8, 2014
Grant date	Jun 9, 2015
Priority date	—
Expiry date	Dec 8, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit containing core transistors and I/O transistors oriented perpendicular to the core transistors is formed by exposing a gate etch mask layer stack through a gate pattern photomask including core transistor gates and oversized I/O transistor gates. Core transistor gate lengths are defined by the gate pattern photomask. A first gate hardmask etch process removes the gate hardmask layer in exposed areas. The process continues with exposing a gate trim mask layer stack through a gate trim photomask. I/O gate lengths are defined by the gate trim photomask. A second gate hardmask etch process removes the gate hardmask layer in exposed areas. A gate etch operation removes polysilicon exposed by the gate hardmask layer to form gates for the core transistors and I/O transistors. The integrated circuit may also include I/O transistors oriented parallel to the core transistors, with gate lengths defined by the gate pattern photomask.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.