Memory circuit and method of forming the same using reduced mask steps
US9054292B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2014 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Apr 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.