Magnetic random access memory integration having improved scaling
US9054297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Sep 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F2, and a uniform thickness of material between the bit lines and the underlying memory elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.