Integrated circuit product yield optimization using the results of performance path testing
US9058034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 6, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.