Cache arrangement
US9058283B2 · kind B2 · utility
1Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Apr 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.