Systems and methods for specifying. modeling, implementing and verifying IC design protocols
US9058463B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2014 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Jan 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended state table-based specifications and the templates in all phases in the design flow, resulting in a tight revision loop of debug, verification, and validation across the phases of the design flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.