Method for estimating the lifespan of a deep-sub-micron integrated electronic circuit
US9058574B2 · kind B2 · utility
3Cited by
8References
8Claims
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Key dates
| Filing date | Jun 30, 2010 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Feb 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for estimating the lifetime of a deep-submicron-generation integrated electronic component, linked to a wear mechanism occurring in previously defined special conditions of use, said component being of a deep submicron type, with very large-scale integration, commercially available off the shelf, wherein one assumes that the same sample population always experiences a failure due to: the most predominant failure mechanism, during the period of useful life, described by an exponential law, and the most critical wear mechanism, represented by a Weibull distribution at the end of the previous period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.