Semiconductor apparatus with boundary scan test circuit
US9058901B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Oct 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor apparatus includes: a receiver configured to receive a plurality of input signals through a plurality of pads; a signal processing unit configured to process the input signals received by the receiver and output the processed signals as a plurality of internal signals; a MUX unit configured to select the plurality of internal signals as a plurality of MUX output or select test input data and a plurality of latch signals as the plurality of MUX output signals in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in response to a latch clock signal; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.