Semiconductor gate structure and method of fabricating thereof
US9059094B2 · kind B2 · utility
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4References
8Claims
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Key dates
| Filing date | Aug 24, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Jul 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.